In fabrication of CMOS devices for VLSI integrated circuits, conductive paths or contacts between first and second conductive films separated by a intervening dielectric layer are formed by defining a via hole or contact hole through the dielectric layer, and then filling the via with conductive material. For example, a dielectric layer of an insulating material such as silicon dioxide, is deposited on a first conductive layer comprising a metal or alloy, such as sputtered aluminium. The insulating layer is selectively masked, and a contact hole or via hole is etched through an exposed region in the insulating layer to expose the underlying conductive layer. A second conductive layer, e.g. sputtered aluminium, is deposited over the insulating layer, with conductive material extending into the via hole, thereby forming a contact between the two conductive layers. Alternatively the via hole may be filled with a plug of conductive material before deposition of the second conductive layer.
Integrated circuits incorporating multilayer conductors may comprise three or more conductive metal layers, each defining metal lines, and separated from the other metal layers by intermetal dielectric layers. In a triple level metal (TLM) structure having three layers of metallization, contact via holes from a first conductive layer to second conductive layer and then from second to third conductive layer, must each pass through at least one layer of intermetal dielectric. To provide a planarized structure having a relatively smooth surface topography, via holes having a depth differential of .gtoreq.5000 .ANG. may be required between the different levels of conductive layers.
The critical dimensions or "cds" of the via hole, that is, the maximum and minimum diameter of the contact area with a conductive layer, are controlled so as to comply with the design rules for semiconductor device structures. In particular, the area defined by the bottom diameter of a via hole should lie within the line width of conductive metal lines. The via hole diameter should provide for sufficient contact area for satisfactory electrical performance, but overlap into other regions which may cause electrical problems should be avoided. To simplify the layout of an integrated circuit, it is preferable that deep and shallow via holes are provided with the same critical dimensions.
Further, in order to provide reliable electrical contacts, it is important that the deposited metal satisfactorily fills the via hole, i.e. provides adequate "step coverage" over the sidewalls, base and edges of the hole without leaving voids or non-uniform regions. It is well known that step coverage of sputtered metal in a deep via hole is improved by tapering of the sidewalls of the via hole, so that the diameter of the via hole is greater at the top than at the bottom. Sidewall tapering of via holes is particularly desirable to obtain adequate step coverage of sputtered metal in via holes having high aspect ratios, i.e. where the depth to width ratio is greater than 0.5.
A number of approaches to tapering sidewalls of via holes of uniform depth are known. Generally dry etching methods based on known isotropic and anisotropic reactive ion etch processes which avoid or minimize surface damage are preferred for defining structures of small geometry. More aggressive etch processes, including sputter etching, are avoided and generally considered unsuitable for defining submicron features such as via holes.
One approach is to provide for a progressive change in etch rate during the process of etching a via hole. For example, an insulating film may be deposited wherein the composition of the insulating film changes with thickness to provide a gradient in etch rate: German Patent DE3914602 discloses deposition of the insulating film as three separate thin layers of different composition and Japanese Patent J56131948 discloses method of depositing an insulating glass layer having a composition gradient. Both these structures provide for a differential etch rate through the thickness of the insulating layer. Another approach is to provide an insulating film of homogeneous composition and to change the etchant composition progressively as etching proceeds, for example, during a reactive ion etching process, by successively changing the composition of reactive gases in stages as the etch process proceeds. As an example, in U.S. Pat. No. 4,814,041 to Auda there is disclosed a process wherein the composition of plasma etchant is changed to provide an increased concentration of oxidizer as etching proceeds. U.S. Pat. No. 4,985,374 to Tsuji discloses use of successive dry etching steps to form a stepwise tapered contact hole and U.S. Pat. No. 4,986,877 to Tachi discloses a temperature gradient during etching to control etch rate as a function of etch depth. However, it will be appreciated that problems arise in such complex multistage processing in maintaining precise control of the etching process to provide via holes of a uniform depth while maintaining cds, and it will be apparent that etching of via holes of large depth differential is impractical by the above-mentioned methods.
Another known method of tapering sidewalls of via holes, e.g. as described in U.S. Pat. No. 4,948,743 to Matsushita, includes providing a dielectric layer which may be heated and caused to reflow around a via hole, thereby rounding off the edges and tending to taper the via hole. Any dielectric which tends to flow into the base of the hole and cover the conductive layer is then removed by reactive ion etching. However, this method has the disadvantage that the resulting sidewall taper is small, and the contact area is not reliably defined by a lithographic step, but depends on the extent and uniformity of the reflow step.
In yet another approach, a tapered sidewall spacer is formed within a steep-sided via hole, by deposition of a film of silicon dioxide or polysilicon which is then anisotropically etched to leave a rounded sidewall spacer having a tapered upper edge, so that the tapered sidewall defines a smaller area contact hole, self-aligned within the original steep-sided hole, as disclosed in U.S. Pat. No. 4,489,481 to Jones and Japanese patent J01273333 to Natori. This technique provides a small taper to the top part of the sidewall, while the bottom part is vertical due to the anisotropy of the reactive ion etching process. To increase the taper, the thickness of deposited oxide has to be increased to more than 5000 .ANG. and consequently requires etching of a correspondingly oversized steep-sided via hole to allow for the thick sidewall spacer. This results in the disadvantage that the minimum metal line width must be large enough to accommodate the oversized steep-sided hole. Furthermore, since the sidewalls define a self-aligned contact area within the steep-sided hole, the bottom diameter of resulting tapered via hole is not directly defined lithographically.
With the exception of the latter method, application of the above-mentioned methods of sidewall tapering to tapering of via holes of different depth, particularly for via holes of large depth differential, would require that shallow via holes and deep via holes be defined in separate sequences of process steps. However, since each sequence itself involves multiple process steps, the above-mentioned methods are impractical and unsatisfactory for etching via holes for multilevel interconnect structures. Consequently, other approaches have been developed for simultaneously etching via holes of different depths for multilevel metal interconnects.
For example, one known method provides for a shallow isotropic etch to provide a tapered (bowl-shaped) shallow portion and then an anisotropic etch from the centre region of the shallow portion of the via hole so as to create a steep-sided, deep portion (i.e. the via hole is shaped like a countersunk screw hole). The metal layer at the bottom of the shallow via holes acts as an etch stop during further etching of the deep via holes down to the deeper level metal. Shallow via holes are predominantly tapered and bowl shaped, with a short, steep-sided deeper portion; deep via holes comprise a corresponding shallow tapered portion plus a deeper steep-sided portion, but consequently the deeper via holes are difficult to fill with sputtered metal of good quality. Although the diameter at the base of the via holes is controlled by the anisotropic etch (i.e. defined by masking/lithography), the isotropic etch depth cannot be deeper than the shallowest via holes without losing the cd of the shallow via holes. Thus, for example, where the depth differential between shallow and deep via holes is .about.5000 .ANG., and the via hole size is less than 1.5 to 2.0 .mu.m, this latter method is not satisfactory.
Another known method for sidewall tapering of multiple depth via holes is based on a multi-step resist erosion process, which creates a via hole having stepped sidewalls. The process involves defining openings in a thick film of resist and anisotropically etching a via hole partially through an insulating film to a first predetermined depth. Then edges of the resist are eroded, for example, by an isotropic etch or sputtering processes to enlarge the hole in the mask, followed by a further anisotropic etch to enlarge the top part of the via hole and cut deeper into the previously etched first centre portion of the via hole, resulting in a step in the sidewall. The process steps of resist erosion and anisotropic etching are repeated until each via hole reaches the required depth and the underlying metal provides an etch stop. In this way via holes of differing depths having staircase-like stepped sidewalls may be created. However, the cd (bottom diameter) of shallow via holes is greater than deep via holes, this difference being significant when the depth differential between shallow and deep via holes is high. Furthermore, the process requires an initial undesirably thick coating of resist followed by multiple process steps and the resulting stepped profile may not provide for satisfactory step coverage.